1. Field of the Invention
The present invention relates to a verification technique for a logic circuit, and particularly relates to a method and system for verifying whether a given logic circuit to be verified properly operates, by creating an operation simulation device for the logic circuit, virtually inputting signals to the simulation device, and checking its outputs against respective expected values.
2. Description of the Related Art
Logic verification systems generally used for verification of logic circuits are composed of a software simulator for simulating a portion of a logic circuit by executing a program on a computer, a hardware emulator for emulating another portion of the logic circuit by using a reconfigurable device, and buffer memory for absorbing the difference in processing speed between the software simulator and the hardware emulator to synchronize them.
For example, a circuit verification system is disclosed in Japanese Laid-open Patent Application No. 2000-215226 (paragraphs 0046 through 0052 and FIGS. 1 and 2) wherein the circuit to be verified is divided into a first portion verified by a hardware emulator and a second portion verified by a software simulator, the clocks of the hardware emulator and the software emulator are synchronized via a communication device, and mutual transfer of data is performed.
Similarly, in U.S. Pat. No. 5,546,562 and Kudlugi et al. (Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor, “A Transaction-based Unified Simulation/Emulation Architecture for Functional Verification,” IEEE Design Automation Conference, 2001, pp. 623-628), FIFO (first-in first-out) memory is provided between a simulator and an emulator, and a signal transmitted from the simulator reaches the emulator via several steps through the FIFO memory. Transmission from the emulator to the simulator on the computer is also performed via FIFO memory in the same manner.
However, the signal transmitted between the hardware emulator and the software simulator passes through the FIFO memory or buffer memory, so there is a possibility that values can vary despite attempting to reference a specific signal value simultaneously from the emulator and the simulator. In other words, strictly speaking, a temporal displacement in processing inevitably occurs between the hardware emulator and the software simulator. Accordingly, when a combination of a computer program and a reconfigurable device is considered as the simulated structure of the logic circuit, the simulated structure and the logic circuit to be verified cannot be said to have exactly the same structure, and the accuracy thereof as a simulation device is low.